Questions tagged [pcie]
PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.
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PCIe to FPGA IC
My company is looking to replace an old design that uses the now obsolete PEX 8311 to go from PCIe to a very custom optical protocol (through an FPGA). My initial plan was to use an FPGA with ...
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How does using an RS232 splitter affect the data transfer speed?
I am converting digital data into an analog signal through the RS232 PCIE card I added to my PC. I have a desire to collect data from up 8 different RS232 connections and I am looking into using an ...
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How are BAR registers handled between end points in PCI Express?
I have a question related to the PCI Express protocol.
I managed to understand most of the features of the PCI Express protocol but could not entirely understand the enumeration process.
I know the ...
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Can I use a 250 nF instead of a 200 nF SMD ceramic capacitor?
Im trying to fix a broken GPU that has a missing 200 nF SMD ceramic capacitor. I found a similar one on a motherboard that has a capacitance of 250 nF. Is it possible to transfer it to fix the GPU?
At ...
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Pinout question: Is this just a PCIe x8 slot in a proprietary card position?
Can anyone tell if this is just a normal PCIe x8 slot in a funny position, or is it also an unusual (incompatible) pinout?
The differential pairs and the number of pins look about right but I thought ...
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Remapping a PCI(e) device when another core is accessing the device
According to PCI(e) specs, is it undefined behavior to access a leaf device from a CPU core when another core is remapping that leaf device to another physical address (e.g. for MMIO on ARM)?
If not, ...
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mPCIE & mSATA 's coupling capacitors
What I am doing is making mPCI-E and mSATA work together in one slot on my Xilinx FPGA. PCIE always only have coupling capacitors on the TX sides(RX sides's capacitors is on the Endpoint Devices), ...
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Mini-PCIe Signal Voltage Levels
Can PERST, CLKREQ, WAKE#, and SMBUS operate at 1.8 V? What I am designing is a mini-PCIe slot compatible with a WWAN card, but this WWAN card can only operate at 1.8 V.
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Studying the PCIe/CXL/CCIX internals at home
Could anybody recommend me a good starting point for self-studying the PCIe internals?
I imagine some kind of an FPGA-based course, covering PCIe endpoint, root complex and switching functionalities. ...
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PCIe power requirements and total capacitance
I'm going straight to the point. In the PCIe CEM specification, regarding to +12V supply, they appear different maximum values of the allowed capacitance depending of the power of the card (10,25 or ...
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What is the purpose of these strange patterns in i/o port panel of GPU card? [closed]
Ref: https://www.techspot.com/article/1988-anatomy-graphics-card/
The left side pattern seems to get it attached to Graphics card slot- but not sure why those flanges are required.
Absolutely no ...
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How to interface two Raspberry Pi CM4 modules and a SOM CN9130 module
I am working on project that requires two Raspberry Pi CM4 modules and a SOM CN9130 module to communicate each other with a data speed of 1GBPS.
Both modules have Ethernet and support the PCIe bus.
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Do PCI Express devices' interrupts always go through a PIC or an APIC?
My Question is PCI/PCIe interrupt path to CPU is through a PIC or an APIC?
https://people.freebsd.org/~jhb/papers/bsdcan/2007/...
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Serial Interfaces - Why USB and PCIe require PHY while e.g. SPI does not require?
I'm trying to understand the reason why USB and PCIe (considering a single lane) can achieve higher data rates than e.g. SPI, I2C, UART.
The reason may be the better handling of signal impairments at ...
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PCIe End-Point configuration for communication with Root Complex
I have an ambiguity regarding the PCIe initial configuration which is performed by the root complex (RC) on the end-points (EP).
Both devices have their own base address registers (BARs). The RC ...
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