Questions tagged [pcie]
PCIe or PCI Express is a high-speed serial computer bus that offers higher speeds and a lower pin count than earlier standards such as PCI that it is designed to replace. Questions should relate to PCIe design issues not general consumer PC / peripheral issues.
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Feeding data stream to FPGA using PCIe [closed]
I am trying to use PCIe with ultrascale+ device and feed the fpga with data stream and send it to another device using PCIe over SFP+ optical cable. However, I don't know how to feed data to the fpga (...
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PCIe digest explanation
In the PCIe standard they wrote the TLP messages may have digest section.
What is the digest of a TLP message described in the PCIe standard?
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PCIe implementation
I was reading about the PCIe stadard, it was mentioned about PCIe PHY, Switched, RootComplex and Bridges that make the PCIe fabric.
I'm trying to connect the dots between the physical hardware and the ...
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CPU to Switch SGMII port with PCIE 2.5Gb
I can't seem to find a 2.5 Gbps Ethernet controller that could be a bridge between the SGMII+ port and PCIe.
this is what I want to do:
I don't want to use PHY (from the copper 2.5G to 2.5G SGMII)
...
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Origin and underlying sense of the term "Posted" in PCIe
When PCI Express replaced the operation of reading directly from a PCI peripheral card over a bus, directly addressing its I/O ports, or performing a configuration cycle on it directly, with instead a ...
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How many lanes of PCIe does Thunderbolt 4 use?
Searching shows that Thunderbolt 4 uses 4 lanes of PCIe 3.0; each lane should contain 3 twisted pairs, two for communication (TX and RX) and one for reference clock. The pinout of Thunderbolt 4 is ...
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Designing a U.2 to M.2 NVMe adapter
I'm considering designing my own U.2 to M.2 converter card to make use of the four U.2 (PCIe 3.0 x4) connectors on my motherboard. Commercial products are available for doing this type of conversion, ...
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Why can't software capture PCIE packets?
I found this question in Stackoverflow and the answers say:
I don't believe so -- from a software viewpoint, PCI-E is quite well
disguised to look like (fast) PCI.
As far as I know, nearly the only ...
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What is the effect of disabling the scrambling on PCIe link stability?
In PCIe base specification document, it is mentioned that
Disabling scrambling is intended to help simplify test and debug equipment...
I am implementing my own custom gen2 PCIe IP in Verilog and I ...
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Problems in understanding PCIe blocks in Xilinx Vivado for Versal devices
AR 1215986 was mentioned on page 7 of PG344, Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide.
In this AR, the author mentioned several components, namely:
PCIe PHY
GT QUAD
...
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PCIe hotplug hardware schematics reference design
I was going through this link, this was very wonderful
Does PCIe hotplug actually work in practice?
Following the above link, I had a question below:
I am looking for a "PCIe hotplug hardware ...
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Can a PCIe Bridge connect to multiple downstream devices using different functions?
My understanding of PCIe bridges is as follows:
A PCIe bridge appears as 1 device on the upstream bus, creates a new bus downstream of it, and whatever connects to the downstream side will appear as ...
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Can someone explain to me why the math for PCIe bandwidth doesn't add up?
Since PCIe g1 x1 is based off PCI 32/66 bandwidth of 2133.33 Mb (...
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PCIe connector overhang
There are precise mechanical requirements for PCIe cards. Along the top edge, there's a 1mm strip where copper and components are not allowed. If you're designing a PCIe card, and have connectors and ...
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Do extra PCIe lanes improve latency?
If you connect a NVME SSD to a PCIe x4 slot it will have a higher maximum bandwith than if you connect it to a 1x or 2x slot. So logically it will transfer large files faster.
But if you never need ...
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PCIe Clock Buffer Daisy Chain
I have a PCIe clock buffer with 4 outputs that I would like to use for more than 4 PCIe devices. My question is can I daisy chain the buffers such that one buffer output is the input to the next ...
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What is the typical NVME SSD abrubt shutdown reaction time for a CC.SHN event until power loss?
The NVME standard under "7.6.2 Shutdown" defines the procedure for an abrupt shutdown event:
...
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Why does PCIe still hold on to 'transfers/second' instead of bits/second or symbols/second?
I think it is kinda all covered in the title. To my (incomplete) knowledge, PCIe is the only modern bus that still expresses its rate in transfers per second. Is there, apart from 'tradition' any ...
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Are PCIe and USB 3.0 the same interface?
I know the title may sound provocative, but I was looking for a PCI hub, and found solutions like these:
I noticed that on the PCIe side, there is actually only one adapter (which looks passive) with ...
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PCIe mode in chip-to-chip communication
In my understanding, the most common PCIe usage is in computer systems which involves a processor host communicating with various endpoints through the PCIe tree topology. In this scenario, we will ...
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OCULink connector pin configuration for Root port and endpoint
We are using an OCUlink connector for the PCIe x4 interface in one of our new design which should support both root port and endpoint. We have a few queries to clarify on the same.
When our board is ...
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PCIe Data Transfer Rate vs Fundamental Frequency
The PCIe Gen 3 standard states that the link works at 8GT/s, while the fundamental frequency of the LVDS signals is maximum 4GHz. To my understanding PCIe doesn't use any sort of DDR technology, so ...
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PCIe Gen4: inter-pair skew: any limits?
For PCIe (and more particularly PCIe Gen 4), is there any recommendation on the maximum inter-pair skew, i.e. the maximum time/length difference between either:
2 TX differential pairs (of different ...
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3.3V in PCIe connector
What is the 3.3V used for in PCIe edge connect?
I have a PCIe connector that has 3.3V and another one that does not have the 3.3V and both are working fine which brings me to wonder why the 3.3V is ...
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PCIe "RefClk" impedance requirements?
I'm designing a very heavy impedance-requiremented PCB, with PCIe v2.
I know TX and RX diffpairs have strict differential ...
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Impedance-critical diff-pair routing
I need to route PCIe RX and TX diffpairs:
I can't change the bottom connector (fits into M.2 KeyE socket), neither the top (M.2 KeyM socket).
Normally, how shall I wire these diffpairs?
It seems I ...
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Frequency of PCIe differential pairs (RX, TX, CLOCK)
I'm planning to design a board for PCIe (v2).
For all impedance matching considerations, there is rule-of-thumb: if you can decrease the trace lengths below 1/10 of the wavelength, you're probably ...
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Designing M.2 socket for SSD
I'm designing a card adaptor which converts from M.2 Key E type to M.2 Key M type (to insert an NVMe SSD into a port designed originally for Wifi cards).
I found some reference design for the M.2 KeyM ...
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Is PCIe IO address space meaningless for ARM-based system?
According to here, the PCI Express TLP (Transaction Layer Packet) can target 4 different address spaces.
My question is about the IO and memory address spaces.
As we know, the PCI specification was ...
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PCI Express Lane Reversal for REFCLK
PCI Express supports lane reversal for the lanes.
Can REFCLK+ and REFCLK- also be swapped? That is, connect REFCLK+ from one device to REFCLK- on the other?
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